Chemical Oxide Removal (“COR”) is a gaseous process known in the art to selectively remove silicon oxides (“SiOx”) by reacting gaseous ammonia (“NH3”) and hydrogen fluoride (“HF”) to produce NH4Fx. The NH3 and HF react with silicon oxide on a semiconductor wafer to form ammonium hexafluorosilicate (“(NH4)2SiF6”). This reaction is referred to herein as a “chemical treatment” and is typically conducted in a reaction chamber. The semiconductor wafer is then transferred to a different chamber and heated, producing nitrogen (“N2”), water (“H2O”), silicon tetrafluoride (“SiF4”), and NH3, which are volatile and evaporate from the surface of the semiconductor wafer. Heating the semiconductor wafer is referred to herein as a “post heat treatment (“PHT”).” Alternatively, the (NH4)2SiF6 is removed using a deionized (“DI”) water rinse. The combination of the chemical treatment and the PHT is referred to herein as the “COR/PHT process.” The COR/PHT process is marketed under the tradename CERTAS® by Tokyo Electron Limited. Additional NH3/HF-based chemistries for etching oxides are marketed by ULVAC Technologies, Inc. (Methuen, Mass.) and Applied Materials, Inc. (Santa Clara, Calif.). Systems for conducting the COR/PHT process are known in the art. These systems include two chambers, one for conducting the chemical treatment and one for conducting the PHT. Semiconductor wafers undergoing the COR/PHT process are transported from one chamber to the other, which adds time to the wafer fabrication process and decreases wafer throughput.
U.S. Pat. No. 6,951,821 discloses using the COR/PHT process to trim an oxide hard mask. The chemical treatment includes exposing the oxide hard mask to NH3 and HF and the PHT includes heating the oxide hard mask to a temperature within a range of 20° C.-200° C. The COR/PHT process etches a thermal oxide at greater than 10 nm per 60 seconds of chemical treatment and tetraethyl orthosilicate (“TEOS”) at greater than 10 nm per 180 seconds of chemical treatment. The COR/PHT process has also been used to selectively remove small amounts (1 nm-30 nm) of silicon oxides, such as a native oxide or a thermal oxide, relative to polysilicon. United States Patent Application Publication No. 2006/0196527 discloses using the COR/PHT process to remove SiO2 in a pre-metal-silicon contact formation cleaning, to remove SiO2 before a silicon epitaxial process, or to remove SiO2 from a polysilicon wafer before depositing a silicide metal.
Furthermore, U.S. Pat. No. 7,091,069 discloses using a plasma or vapor of HF and NH3 to remove a sacrificial oxide layer on a silicon-on-insulator (“SOI”) metal oxide semiconductor field effect transistor (“MOSFET”). U.S. Pat. No. 6,656,824 discloses using a plasma or vapor of HF and NH3 to remove a sacrificial oxide layer in a MOSFET. The plasma or vapor of HF and NH3 produces undercuts beneath silicon spacers formed on sidewalls of a dielectric layer of the MOSFET. U.S. Pat. No. 6,838,347 discloses etching concave portions of an oxide hardmask at a reduced rate relative to convex portions using a plasma or vapor of HF and NH3. Additionally, attempts have been made to reduce line defects on oxide-based mask lines by eliminating undesirable curves and protrusions, such as whiskers, using the COR/PHT process.
United States Patent Application Publication No. 2006/0051966 discloses a method of removing oxides from a substrate and cleaning a processing chamber used to remove the oxides. The oxides are removed using a dry etchant that includes a mixture of NH3 and nitrogen trifluoride (“NF3”). A plasma of the NH3/NF3 mixture is generated and reacts with the oxides, forming (NH4)2SiF6. To remove the (NH4)2SiF6, the substrate is elevated in the processing chamber and annealed using a heated distribution plate, which provides thermal energy to dissociate the (NH4)2SiF6 into volatile species. The processing chamber is periodically cleaned using high heat conductivity gases and heat or using a plasma.
Accordingly, what is needed in the art are methods of removing silicon oxides from semiconductor wafers enabling improved wafer throughput.